In wire line communication between boards, such as servers, and between parts mounted on boards, the data rate of transmitting and receiving signals is increasing. In reception circuits that receive such high-speed data, asynchronous sampling, in which input data is sampled not in synchronization with the phase of the input data, is more effective than synchronous sampling, in which input data is sampled in synchronization with the phase of the input data.
An asynchronous sampling reception circuit interpolates data asynchronously sampled, thereby generating reception data. As a conventional technique, there has been proposed a technique in which, after asynchronous sampling, analog linear interpolation processing is performed, and, by using an analog-to-digital (A/D) converter with a low resolution, it is determined whether data is “1” or “0”.
Y. Doi et al., “32 Gb/s Data-Interpolator Receiver with 2-Tap DFE in 28 nm CMOS”, IEEE International Solid-State Circuits Conference, February 2013 is an example of the related art.